The present invention relates to lateral MISFETs (metal-insulator-semiconductor field effect transistors) having a trench structure, and a method of manufacturing the lateral MISFETs. The lateral MISFET, that exhibits a high breakdown voltage and a low on-resistance, is used as an individual device or integrated into a power IC incorporated into an electronic instrument, an IC for driving a motor, an IC for driving a liquid crystal display, etc.
A power MOSFET (metal-oxide-semiconductor field effect transistor), one of the MISFETs, is outstanding by virtue of its low loss and high switching speed among the power semiconductor devices. However, the power MOSFET has a problem in reducing its on-resistance. Since the power MOSFET is a single-carrier (electron or hole) device, the conductivity thereof is not modulated by minority carrier injection. On the other hand, techniques for forming trenches in a semiconductor surface are adopted in various ways inclusive of aiming at on-resistance reduction in the semiconductor devices. And, various semiconductor devices which have a trench structure therein have been proposed recently.
FIG. 13 is a cross section of a part of a vertical trench MOSFET. FIG. 13 shows a unit cell of the MOSFET that includes a half of a trench. Many actual MOSFETs adopt a structure that connects in parallel many such unit cells arranged alternately in a mirror symmetry. The actual MOSFET requires a peripheral portion that sustains the breakdown voltage thereof in addition to the current carrying portion shown in FIG. 13. Since the general structures may be adopted to the peripheral portion, explanation of the peripheral portion will be omitted. In FIG. 13, a trench 1302 is formed from a first major surface of a semiconductor substrate 1301. A p-base region 1308 is formed beside the trench 1302. An n-source region 1309 is formed in a part of the surface layer of the base region 1308. An n-drain layer 1303 is formed on a second major surface of the semiconductor substrate 1301. The side face of the trench 1302 is covered with a thin gate oxide film 1306. A gate electrode 1307 is buried in the trench 1302. A source electrode 1312 that contacts commonly with the n-source region 1309 and the p-base region 1308 is disposed on the first major surface, from that the trench 1302 is formed, of the semiconductor substrate 1301. A drain electrode 1313 is disposed on the back surface of the n-drain layer 1303. As shown in the figure, the source electrode 1312 may be extended over the gate electrode 1307 with an inter-layer insulation film 1311 inserted inbetween. When a positive voltage is applied to the gate electrode 1307 of the device of FIG. 13, a channel inverted to n-type is created in the surface layer of the p-base region 1308 beneath the gate electrode 1307, and the n-source region 1309 and the n-drain region 1303 are electrically connected with one another.
The vertical trench MOSFET of FIG. 13 facilitates reducing the cell pitch, i.e. the dimensions of the unit cell, since the MOS gate structure thereof is disposed in the trench. Therefore, the vertical trench MOSFET of the figure facilitates reducing the on-resistance thereof by arranging more unit cells in a unit area. However, since the drain electrode 1313 is disposed on the back surface of the semiconductor substrate 1301, the MOSFET of FIG. 13 has drawbacks in integration with the control and protection circuits into a monolithic structure, in integration of a plurality of the MOSFETs into a single chip, and in adoption of a multi-drain structure.
In contrast to the vertical MOSFETs, lateral MOSFETs in which the source and drain electrodes are disposed on the same side of the semiconductor substrate facilitate integration with the control and protection circuits into a monolithic structure, integration of a plurality of the MOSFETs into a single chip, and adoption of a multi-drain structure. As far as the present inventors know, two lateral MOSFETs which have a trench structure have been reported so far. The first example is a top-drain-trench type RESURF DMOS transistor construction disclosed in the Japanese Unexamined Laid Open Patent Application (Koukai) No. H06-97450. The top-drain-trench type RESURF DMOS has a trench, on the first side thereof is formed a p-base region. An n-source region is formed in a part of the surface layer of the p-base region. The first side of the trench on which the n-source region is formed is covered with a thin gate oxide film. A gate electrode is buried in the trench. An n-drain drift region is formed on the second side of the trench opposed to the first side. The second side of the trench is covered with a thick oxide film. On the semiconductor layer located on the side opposed across the trench to the side on which the n-source region is formed, an n-drain region is formed in contact with the n-drain drift region. Thus, the top-drain-trench type RESURF DMOS increases integrated unit cells to reduce the on-resistance thereof by forming the MOS gate on the side face of the trench.
The second example of the lateral trench MOSFET is a TDD (trench-drain-double diffusion) MOSFET structure (cf. Sakai et al., Technical Report, EDD-92-92, Japanese Institute of Electrical Engineers). FIG. 14 is a cross section of the TDD MOSFET. Referring now to FIG. 14, an epitaxial substrate has an n+ substrate 1419 on which is laminated an n-type semiconductor layer 1401. A p-base region 1408 and an n-source region 1409 are self-aligned by double diffusion in the surface layer of the epitaxial substrate. A p-contact region 1410, with a higher impurity dose than the p-base region 1408, is formed in the surface layer portion of the p-base region 1408 in which the n-source region 1409 is not formed. A poly-crystalline silicon gate electrode 1407 is disposed above the portion of the p-base region 1408, with a gate oxide film 1406 inserted inbetween, extending between the n-type semiconductor layer 1401 and the n-source region 1409. A source electrode 1412 is disposed in common contact with the n-source region 1409 and the p-contact region 1410. A trench 1402 is dug in a drain region. After forming an n-drain region 1403 by diffusion from the inside wall of the trench 1402, a drain electrode 1413 is disposed on the bottom and side faces of the trench 1402. The side and upper parts of the gate electrode 1407 is covered with an inter-layer insulation film 1411 to insulate the gate electrode 1407 from the source electrode 1412. By applying a positive bias voltage to the gate electrode 1407, a channel is created in the surface layer of the p-base region 1408, and the n-drain region 1403 and the n-source region 1409 are electrically connected with one another. The TDD MOSFET of FIG. 14 increases the contact area and reduces the contact resistance of the drain electrode 1413 by forming the trench 1402 in the drain region. By these means, the TDD MOSFET has reduced the on-resistance thereof by 5%.
In the first device structure of the conventional lateral trench MOSFETs, it is hard to secure the uniformity and reliability of the gate oxide film because of the etching damage at trench formation and the stress exerted to the corner of the trench at oxidizing to form the gate oxide film. Moreover, since two kinds of gate oxide films should be formed on the right and left halves of the trench respectively, the process for manufacture is inevitably complicated. The second example of the conventional lateral trench MOSFETs avoids the problems pointed out above, since the gate of the MOS structure is formed in a portion in which the trench is not formed. However, since the breakdown voltage of the device is determined by the distance LD of FIG. 14 between the gate and drain, the adoption of the trench structure is not expected to contribute to integrated unit cell increase.